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Layout optimization by pattern modification
1990
Conference proceedings on 27th ACM/IEEE design automation conference - DAC '90
This paper introduces a new and practical approach to several layout optimization problems. A novel two-dimensional pattem generator, in connection with a set of routing and placement transformations, is employed to efficiently solve problems ranging from Wire Crossing Minimization and Topological Via Minimization to Minimum Steiner Tree Optimization and IO Alignment. The expected running time is O(n1ogn) and the space requirement is O(n), where n is the number of layout objects. The system is
doi:10.1145/123186.123424
dblp:conf/dac/Hojati90
fatcat:jw5w4fg5ibainmnbfdzqb73k5i