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Single-ended SRAM with high test coverage and short test time
2000
IEEE Journal of Solid-State Circuits
The advantages of low power dissipation and smaller chip area for single-ended SRAM's are well known. In this paper, we present the configuration and test strategy of a single-ended, six-transistor SRAM. The benefits of short test time, no retention test, and high test coverage are verified. The goals of low power, high quality control, and short test time of the full CMOS SRAM can be achieved. Index Terms-High test coverage, IFA-9, retention fault, singleended cell, SRAM.
doi:10.1109/4.818928
fatcat:jfmtudaejffdpgiceqd2b3gmqu