Wirelength reduction by using diagonal wire

Charles Chiang, Qing Su, Ching-Shoei Chiang
2003 Proceedings of the 13th ACM Great Lakes Symposium on VLSI - GLSVLSI '03  
We study the octilinear Steiner tree to evaluate the rectilinear Steiner tree based router. First, we give the worst and average case wirelength for rectilinear routing and octilinear routing for two terminals net. Next, we show the octilinear Steiner trees have smaller wirelength reduction for multiterminal net than that of rectilinear Steiner tree. Then, we propose an O(|V | + |E|) algorithm to construct an isomorphic octilinear Steiner tree from a rectilinear Steiner tree G = (V, E) and
more » ... G = (V, E) and prove the wirelength of the isomorphic octilinear Steiner tree is the lower bound. In the end, we show two types of experiment of wirelength reduction results by using diagonal wire The octilinear Steiner tree reduces 9.201% and 6.63% of the wirelength over rectilinear Steiner tree on a set of nets generated at random and on 15 VLSI designs, respectively.
doi:10.1145/764808.764836 dblp:conf/glvlsi/ChiangSC03 fatcat:2wrnrw5dh5a57a3srjpzbpbvca