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Proceedings of the 2002 international symposium on Physical design - ISPD '02
Traditionally, interconnect effects are taken into account during logic synthesis via wireload models, but their ineffectiveness for DSM technologies has been demonstrated and various physical synthesis approaches have been spawned to address the problem. Of particular interest is that logic block size is no longer dictated exclusively by total cell area, yet synthesis optimization objectives are aimed specifically at minimizing the number and size of cells. Methodologies that incorporatedoi:10.1145/505418.505421 fatcat:hl7qj3mxe5abzient4jlyup6ge