FPGA IMPLEMENTATION OF COEFFICIENT DECIMATED POLYPHASE FILTER BANK STRUCTURE FOR MULTISTANDARD COMMUNICATION RECEIVER

P Devi, R Bhuvaneshwaran
2014 unpublished
Coefficient decimated polyphase FIR filter bank structure implemented for receiving narrow band channels effectively in multistandard environment. Reonfigurability in multirate filtering is required to design a prototype filter bank structure for selecting the distinct polyphase sub filters and taps for different standards. Coefficient decimation (CD) based filter bank can offer a good trade-off between reconfigurability and low complexity which satisfy most of the requirements for SDR
more » ... . This paper proposed a method of filter bank technique which reduces the overall complexity of the design. The proposed filter structure has been synthesized on 0.18µm CMOS technology single core Field programmable gate array. Synthesis report proved the reduced device utilization for the proposed structure.
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