A 1.5 GHz All-Digital Spread-Spectrum Clock Generator

Sheng-You Lin, Shen-Iuan Liu
2009 IEEE Journal of Solid-State Circuits  
An all-digital spread-spectrum clock generator (SSCG) has been fabricated in a 0.18 m CMOS process. The analysis and design of this all-digital SSCG is presented. A mixed-signal phase and frequency detector is adopted to reduce the jitter, eliminate a digital adder, and also reduce latency. A Vernier time-to-digital converter (TDC) with time amplifiers is realized to enhance the timing resolution of the TDC and to track the frequency modulation in the SSCG. A digitally controlled oscillator
more » ... lled oscillator with a resolution enhancement circuit is also presented. The measured electromagnetic interference reduction is 10.48 dB. The measured peak-to-peak jitter and rms jitter are 28.4 ps and 4 ps, respectively, at 1.5 GHz. Index Terms-All-digital phase-locked loop, electromagnetic interference, phase-locked loop, spread-spectrum clock generator, time-to-digital converter.
doi:10.1109/jssc.2009.2031577 fatcat:oabzz235x5enzlxzzzhj3dvqui