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An all-digital spread-spectrum clock generator (SSCG) has been fabricated in a 0.18 m CMOS process. The analysis and design of this all-digital SSCG is presented. A mixed-signal phase and frequency detector is adopted to reduce the jitter, eliminate a digital adder, and also reduce latency. A Vernier time-to-digital converter (TDC) with time amplifiers is realized to enhance the timing resolution of the TDC and to track the frequency modulation in the SSCG. A digitally controlled oscillatordoi:10.1109/jssc.2009.2031577 fatcat:oabzz235x5enzlxzzzhj3dvqui