Performance estimation of multistreamed, superscalar processors

W. Yamamoto, M.J. Serrano, A.R. Talcott, R.C. Wood, M. Nemirosky
1994 Proceedings of the Twenty-Seventh Hawaii International Conference on System Sciences HICSS-94  
Multistreamed processors can significantly improve processor throughput by allowing interleaved execution of instructions from multiple instruction streams. In this paper, we present an analytical modeling technique to evaluate the effect of dynamically interleaving additional instruction streams within superscalar architectures. Using this technique, estimates of the instructions executed per cycle (IPC) for a processor architecture are quickly calculated given simple descriptions of the
more » ... ad and hardware characteristics. To validate this technique, estimates of the SPEC89 benchmark suite obtainedfrom the model are compared to results from a hardware simulator. Our results show the technique produces accurate estimates with an average deviation of -4% from the simulation results. Finally, we demonstrate that as the number of functional units increases, multistreaming is an effective technique to expbir these additional resources.
doi:10.1109/hicss.1994.323172 fatcat:fai3ploxjja3fifqufwzcfzcla