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DDCache: Decoupled and Delegable Cache Data and Metadata
2009
2009 18th International Conference on Parallel Architectures and Compilation Techniques
In order to harness the full compute power of manycore processors, future designs must focus on effective utilization of on-chip cache and bandwidth resources. In this paper, we address the dual goals of (1) reducing on-chip communication overheads and (2) improving on-chip cache space utilization resulting in larger effective cache capacity and thereby potentially reduced off-chip traffic. We present a new cache coherence protocol that decouples the logical binding between data and metadata in
doi:10.1109/pact.2009.24
dblp:conf/IEEEpact/HossainDH09
fatcat:xiumut6errhgnnihu5xcnvcojq