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Characterizing speed-independence of high-level designs
Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems
This paper characterizes the speed-independence of high-level designs. T h e characterization is a condition o n the design description ensuring that the behavior of the design i s independent of the speeds of its components. T h e behavior of a circuit is modeled as a transition system, that allows data types, and internal as well as external non-determinism. This makes it possible to verify the speed-independence of a design without providing a n explicit realization of the environment. T h e
doi:10.1109/async.1994.656285
dblp:conf/async/KishinevskyS94
fatcat:5ob2wwunj5ccrdb4lae67p4dya