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Conflict graph based hardware transactional memory
2010
2010 3rd International Conference on Computer Science and Information Technology
This paper proposes a novel transactional memory design: conflict graph based hardware transactional memory. It allows two conflicting transactions both to commit if they do not violate the condition of serializability. Simulation results show that conflict graph based hardware transactional memory outperforms the state-of-art transactional memory system.
doi:10.1109/iccsit.2010.5563895
fatcat:hkzzagilmral3bdikhpvkscuma