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Lecture Notes in Computer Science
A fault-tolerant routing algorithm in Network-on-Chip architectures provides adaptivity for on-chip communications. Adding faulttolerance adaptivity to a routing algorithm increases its design complexity and makes it prone to deadlock and other problems if improperly implemented. Formal verification techniques are needed to check the correctness of the design. This paper performs formal analysis on an extension of the link-fault tolerant Network-on-Chip architecture introduced by Wu et al thatdoi:10.1007/978-3-319-10702-8_4 fatcat:naxfhztyqzb73feg5bwdr2frbe