Instruction Issue Logic in Pipelined Supercomputers

Weiss, Smith
1984 IEEE transactions on computers  
Basic principles and design tradeoffs for control of pipelined processors are first discussed. We concentrate on register-register architectures like the CRAY-1 where pipeline control logic is localized to one or two pipeline stages and is referred to as "instruction issue logic." Design tradeoffs are explored by giving designs for a variety of instruction issue methods that represent a range of complexity and sophistication. These vary from the CRAY-1 issue logic to a tersion of Tomasulo's
more » ... n of Tomasulo's algorithm, first used in the IBM 360191 floating point unit. Also studied are Thornton's "scoreboard" algorithm used on the CDC 6600 and an algorithm we have devised. To provide a standard for comparison, all the issue methods are used to implement the CRAY-1 scalar architecture. Then, using a simulation model and the Lawrence Livermore Loops compiled with the CRAY Fortran compiler, performance results for the various issue methods are given and discussed.
doi:10.1109/tc.1984.1676375 fatcat:edjw2ezdjjarzklxwjm5misife