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2003 Design, Automation and Test in Europe Conference and Exhibition
This paper describes a methodology for analog layout synthesis based on the automatic generation of an equivalent composite transistor with the same DC current characteristics of the transistors in the electrical schematic. The tool serves a dual purpose: i) the layout synthesis of analog blocks over a digital sea-of-gates prediffused array, and ii) the generation of custom associations of transistors for matched common-source input pairs and current mirrors. The LIT tool generates the layoutdoi:10.1109/date.2003.1253756 fatcat:nxdx72uv6bedpoaqycz2vh2up4