Power-efficient and fault-tolerant circuits and systems

Lei He, Yu Hu
2009 2009 IEEE 8th International Conference on ASIC  
As devices become smaller, circuits and systems are more vulnerable to soft errors caused by radiation and other environmental upsets. Fault tolerance measured by mean time to failure (MTTF) is desired, especially if no extra area, power and delay and little change of the existing design flow are introduced. Using FPGA as a testbed, this paper first presents fault tolerance techniques applying (1) logic don't care and path re-convergence (ROSE) and (2) in-place logic re-writing (IPR). Both
more » ... ase MTTF by 2X with little or no overhead. Particularly, IPR does not change circuit placement and routing, and can be readily used with the existing industrial design flow. It also leads to a self evolution method to enhance fault tolerance for FPGA based circuits and systems. The ideas presented in the paper can be extend to handle regular logic fabrics, which are natural to nanotechnologies and are also preferred by design for manufacturability (DFM) in scaled CMOS technologies 1 .
doi:10.1109/asicon.2009.5351304 fatcat:uw77tpd5dzdqpe55xvj4yrt2ji