COOL CHIPS 2020 Final Program

2020 2020 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)  
Among the many emerging domains, Artificial Intelligence (AI) based applications have begun to permeate everywhere, and as such, ensuring their secure operation has become paramount. Meanwhile, hardware security is fast becoming a pressing problem with the growth of security attacks targeting processors and their peripherals. Therefore, hardware researchers have to better understand their designs and guard these critical AI applications against security flaws. In this talk, we will first visit
more » ... he fundamental problems surrounding sensitive information leakage that dominate security research landscape and has the potential to hamper AI applications. More recently, timing channels have emerged as one of the most dangerous forms of information leakage leaving no physical evidence of an attack. We will explore the basic solutions needed to alleviate these timing channels that includes our early work to detect them on oft-used hardware structures. We will then go over some of our recent research findings that aims to find stronger indicators for timing channels. Next, we will see how more sophisticated adversaries may target inter-cache hardware mechanisms such as cache coherence protocols. Finally, we will wrap up the talk with some of my thoughts on how to design low-cost, hardware-software cooperative solutions to effectively defend against these attacks and how they could be customized for the AI domain. 10:30-11:00 Break 11:00-12:30 Special Invited Lecture 2 Co-chairs: Takatsugu Ono (Kyushu Univ.), Hiroki Matsutani (Keio Univ.) 11:00-12:30 Using AI to Bridge the Gap Between AI Models and the Hardware of Today and Tomorrow Abstract: There is an increasing need to bring machine learning to a wide diversity of hardware devices. Current frameworks rely on vendor-specific operator libraries and optimize for a narrow range of server-class GPUs. Deploying workloads to new platforms -such as mobile phones, embedded devices, and accelerators (e.g., FPGAs, ASICs) -requires significant manual effort. In this talk I will present our work on the TVM stack, which exposes graph-level and operator-level optimizations to provide performance portability to deep learning workloads across diverse hardware back-ends. TVM solves optimization challenges specific to deep learning, such as high-level operator fusion, mapping to arbitrary hardware primitives, and memory latency hiding. It also automates optimization of low-level programs to hardware characteristics by employing a novel, learning-based cost modeling method for rapid exploration of code optimizations. To address threat of changes in algorithms, models, operators, or numerical systems threaten to the viability of specialized hardware accelerators, we developed VTA, a programmable xii April 16, 2020 Abstract: Disruptive evolutions of digital transformation in industries and societies are invoking technology challenges to embedded processors and their solutions. After introducing key issues and criteria of those challenges in several market segments such as automotive, industry and infrastructure, countermeasure examples are to be explained showing how to address those issues clearing the criteria such as efficiencies (performance per power & cost), effective performance in real use cases, system robustness, easy-to-use/reuse SW and development environment. A real solution example with high-end processors and micro controllers for a mission critical application is introduced to summarize each technology explained in the presentation. Abstract: NAND flash memory expanded its market and application and changed xiv 15:00-15:25 MMT-based Multi-channel Video Transmission System with Synchronous Processing Architecture Yasuhiro Mochida, Takahiro Yamaguchi, Ken Nakamura (NTT) 15:25-15:45 Break 15:45-16:35 16:35-16:55 Break 16:55-17:45 Session VIII: Low Power Processors Co-chairs: Kotaro Shimamura (Hitachi), Fumio Arakawa (Nagoya Univ.), Takumi Uezono (Hitachi) 16:55-17:20 A 0.4-0.9V, 2.
doi:10.1109/coolchips49199.2020.9097640 fatcat:gey3ljttvzev7kjognaskbhuf4