HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection

R.S. Chakraborty, S. Bhunia
2009 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Hardware intellectual-property (IP) cores have emerged as an integral part of modern system-on-chip (SoC) designs. However, IP vendors are facing major challenges to protect hardware IPs from IP piracy. This paper proposes a novel design methodology for hardware IP protection using netlist-level obfuscation. The proposed methodology can be integrated in the SoC design and manufacturing flow to simultaneously obfuscate and authenticate the design. Simulation results for a set of ISCAS-89
more » ... k circuits and the advanced-encryption-standard IP core show that high levels of security can be achieved at less than 5% area and power overhead under delay constraint.
doi:10.1109/tcad.2009.2028166 fatcat:kxzzulxprnb23llviw6yzqyehm