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Register promotion by sparse partial redundancy elimination of loads and stores
1998
Proceedings of the ACM SIGPLAN 1998 conference on Programming language design and implementation - PLDI '98
An algorithm for register promotion is presented based on the observation that the circumstances for promoting a memory location's value to register coincide with situations where the program exhibits partial redundancy between accesses to the memory location. The recent SSAPRE algorithm for eliminating partial redundancy using a sparse SSA representation forms the foundation for the present algorithm to eliminate redundancy among memory accesses, enabling us to achieve both computational and
doi:10.1145/277650.277659
dblp:conf/pldi/ChowKLLT98
fatcat:mf3u5o7mnvajlhf4bf5jarqxri