A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2008; you can also visit the original URL.
The file type is
A power management unit (PMU) architecture is proposed for the domain-specific low power management with dynamic voltage and frequency scaling. The PMU continuously co-locks and dynamically varies the supply voltage and the clock frequency from 89 MHz to 200 MHz and from 1.0 V to 1.8 V , respectively, in less than 40µs. A 32bit RISC processor is used as power management target device. The PMU, 0.36mm 2 with 0.18-µm CMOS process, consumes 5mW, and shows -100dBm/Hz phase noise of clock and 160mVdoi:10.1109/iscas.2007.378516 dblp:conf/iscas/LeeNSCY07 fatcat:v4awjtgs2rdkherbrpxwvvonze