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Hardware counters are a fundamental building block of modern high-performance processors. This paper explores two applications of probabilistic counter updates, in which the output of a pseudo-random number generator decides whether to perform a counter increment or decrement. First, we discuss a probabilistic implementation of counter hysteresis, whereby previously proposed branch confidence and criticality predictors can be reduced in size by factors of 2 and 3, respectively, with negligibledoi:10.1109/hpca.2006.1598118 dblp:conf/hpca/RileyZ06 fatcat:fy3llhaejba3tl4yjja5rv5f6a