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A Compact CMOS Face Detection Architecture Based on Shunting Inhibitory Convolutional Neural Networks
2008
4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008)
In this paper, we present a compact, low cost, real-time CMOS hardware architecture for face detection. The proposed architecture is based on a VLSI-friendly implementation of Shunting Inhibitory Convolutional Neural Networks (SICoNN). Reported experimental results show that the proposed architecture can detect faces with 93% detection accuracy at 5% false alarm rate. A VLSI Systolic architecture was considered to further optimize the design in terms of execution speed, power dissipation and
doi:10.1109/delta.2008.66
dblp:conf/delta/ZhangBBB08
fatcat:u74txo57nbgafe6qnmagt7xpey