Technology assessment of Si and III-V FinFETs and III-V tunnel FETs from soft error rate perspective

Huichu Liu, Matthew Cotter, Suman Datta, Vijay Narayanan
2012 2012 International Electron Devices Meeting  
Sea-level soft error performance has been investigated for Si FinFET, III-V FinFET and III-V Heterojunction Tunnel FET in this paper. Transient error generation and transient current profiles in these devices have been evaluated using device simulation. Based on the critical charge extraction for each emerging device-based circuit, the electrical and latching window masking effects have been studied. Below 0.5V, III-V FinFET logic shows reduced soft error rate (SER) compared to Si FinFET. HTFET
more » ... shows reduced SER for both SRAM and logic compared to Si and III-V FinFET over the evaluated voltage range of 0.3V-0.6V.
doi:10.1109/iedm.2012.6479103 fatcat:wroso6zjnfbpxdngb5fwwurzzq