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Product cost is a major driver in the consumer electronics market, which is characterized by low profit margins and the use of core-based system-on-chip (SoC) designs. Packaging has been recognized as a significant contributor to the product cost for such SoCs. To reduce packaging cost and the test cost for packaged chips, wafer-level testing (wafer sort) is used in the semiconductor industry to screen defective dies. However, since test time is a major practical constraint for wafer sort, evendoi:10.1109/test.2006.297646 dblp:conf/itc/BahukudumbiC06 fatcat:bwwcz6z3e5hqbl3qlskpgyniiy