Software-managed address translation

B. Jacob, T. Mudge
<i title="IEEE Comput. Soc. Press"> <a target="_blank" rel="noopener" href="" style="color: black;">Proceedings Third International Symposium on High-Performance Computer Architecture</a> </i> &nbsp;
In this paper we explore software-managed address translation. The purpose of the study is to specify the memory management design for a high clock-rate PowerPC implementation in which a simple design is a prerequisite for a fast clock and a short design cycle. We show that softwaremanaged address translation is just as efficient as hardware-managed address translation, and it is much more flexible. Operating systems such as OSF/1 and Mach charge between 0.10 and 0.28 cycles per instruction
more &raquo; ... ) for address translation using dedicated memory-management hardware. Software-managed translation requires 0.05 CPI. Mechanisms to support such features as shared memory, superpages, sub-page protection, and sparse address spaces can be defined completely in software, allowing much more flexibility than in hardware-defined mechanisms.
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="">doi:10.1109/hpca.1997.569652</a> <a target="_blank" rel="external noopener" href="">dblp:conf/hpca/JacobM97</a> <a target="_blank" rel="external noopener" href="">fatcat:2lzv2hlqsfebjjxnyf4uu2wwyq</a> </span>
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