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Proceedings. Frontiers '99. Seventh Symposium on the Frontiers of Massively Parallel Computation
In this paper, we present efficient VLSI layouts of several hypercubic networks. We show that an N-node hypercube and an N-node cube-connected cycles (CCC) graph can be laid out in 4N 2 =9 + oN 2 and 4N 2 =9 log 2 2 N + oN 2 = log 2 N areas, respectively, both of which are optimal within a factor of 1:7 + o1. We introduce the multilayer grid model, and present efficient layouts of hypercubes that use more than 2 layers of wires. We derive efficient layouts for butterfly networks, generalizeddoi:10.1109/fmpc.1999.750589 fatcat:j5bnhjac7jer7lfb2ub7bkbcba