Efficient VLSI layouts of hypercubic networks

Chi-Hsiang Yeh, E.A. Varvarigos, B. Parhami
1999 Proceedings. Frontiers '99. Seventh Symposium on the Frontiers of Massively Parallel Computation  
In this paper, we present efficient VLSI layouts of several hypercubic networks. We show that an N-node hypercube and an N-node cube-connected cycles (CCC) graph can be laid out in 4N 2 =9 + oN 2 and 4N 2 =9 log 2 2 N + oN 2 = log 2 N areas, respectively, both of which are optimal within a factor of 1:7 + o1. We introduce the multilayer grid model, and present efficient layouts of hypercubes that use more than 2 layers of wires. We derive efficient layouts for butterfly networks, generalized
more » ... ercubes, hierarchical swapped networks, and indirect swapped networks, that are optimal within a factor of 1 + o1. We also present efficient layouts for folded hypercubes, reduced hypercubes, recursive hierarchical swapped networks, and enhanced-cubes, which are the best results reported for these networks thus far.
doi:10.1109/fmpc.1999.750589 fatcat:j5bnhjac7jer7lfb2ub7bkbcba