The widening gap between CPU complexity and verification capability is becoming increasingly more salient. It is impossible to completely verify the functionality of a modern microprocessor before shipping, much less before tape out. Recent studies indicate that the majority of errors in these designs are centered on control and forwarding logic [9] . To address this problem, we present Chico, an efficient approach to on-chip hardware correctness that specifically targets escaped design errors

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... n these high risk functional blocks. Our solution includes an on-chip checker block that monitors the correctness of potential data dependencies and program order of the executed instructions before they are allowed to commit. If this online checker detects a mismatch, the processor's exception handler is invoked, reconfiguring the system to a known-correct, formally-verified mode of operation which can correctly re-execute and commit the faulty instruction. The processor can then resume its normal, high throughput mode of operation. In our experimental setup, we have implemented Chico in an out-of-order processor design and evaluated its performance impact on 11 distinct buggy variants of the design running SPECint benchmarks. Our results indicate that Chico can overcome the errors present in these buggy designs at a minimal performance cost, ranging from less than 1% up to 4%. In addition, we evaluated Chico's area cost and found it to be an order of magnitude smaller than other popular solutions such as DIVA[10], with an area impact of less than 3% for our experimental processor. Our approach is novel in that it shows no appreciable performance degradation on a correct design, and it is a low complexity, area-frugal solution compared to previous work.