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This paper presents an implementation of a high-performance network application layer parser in FPGAs. At the core of the architecture resides a pattern matcher and a parser. The pattern matcher scans for patterns in high-speed streaming TCP data streams. The parser core augments each pattern found with semantic information determined from the patterns location within the data stream. The packet payload parser can provide a higher level of understanding of a data stream for many networkdoi:10.1109/fpl.2006.311308 dblp:conf/fpl/MoscolaCL06 fatcat:hjuzhdyz7vbvhbiuplge4rtbcm