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Performance Evaluation for System-on-Chip Architectures using Trace-based Transaction Level Simulation
2006
Proceedings of the Design Automation & Test in Europe Conference
The ever increasing complexity and heterogeneity of modern System-on-Chip (SoC) architectures make an early and systematic exploration of alternative solutions mandatory. Efficient performance evaluation methods are of highest importance for a broad search in the solution space. In this paper we present an approach that captures the SoC functionality for each architecture resource as sequences of trace primitives. These primitives are translated at simulation runtime into transactions and
doi:10.1109/date.2006.244111
dblp:conf/date/WildHO06
fatcat:qy7ub4jyg5hshnr6qo55bz44b4