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Efficient VLSI Implementation of N/N Integer Division
2005 IEEE International Symposium on Circuits and Systems
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This paper presents an efficient implementation of an N -bit by N -bit combinational divider using the nonrestoring shift-subtract algorithm. A theoretical speed-up of 50% for an N/N -bit divider, compared to a merely truncated array implementation, is demonstrated. In practice, delay reduction of 25%-35% can easily be achieved with very little area overhead.
doi:10.1109/iscas.2005.1464677
dblp:conf/iscas/KhooW05
fatcat:5fuf2u3iyfbpthv55oyxm23eqi