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Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlike transistors, have not followed the same trend. Designing 3D stack architectures is a recently proposed approach to overcome the power consumption and delay problems associated with the interconnects by reducing the length of the wires going across the chip. However, 3D integration introduces serious thermal challenges due to the high power density resulting from placing computational units ondoi:10.1109/date.2009.5090885 dblp:conf/date/CoskunAARL09 fatcat:zgjy6b6glnbhdgayxjkbkkzaim