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Simulation and Synthesis of Majority Logic Decoder/Detector for EG-LDPC Codes
2014
International Journal of Computer Applications
In this paper, a technique was proposed to protect memory cells, which are more susceptible to soft errors. These memory cells are to be protected with effective error correction codes. MLD codes are suitable for memory applications because of their ability to correct large number of errors. Conversely, they increase the average latency of the decoding process because it depends upon the code size that impacts memory performance. A method was proposed as majority logic decoder/detector of
doi:10.5120/18225-9376
fatcat:lqh25pcqsbfsjmwubsdw22cnum