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Low-Latency QC-LDPC Encoder Design for 5G NR
2021
Sensors
In order to meet the low latency and high throughput requirements of data transmission in 5th generation (5G) New Radio (NR), it is necessary to minimize the low power encoding hardware latency on transmitter and achieve lower base station power consumption within a fixed transmission time interval (TTI). This paper investigates parallel design and implementation of 5G quasi-cyclic low-density parity-check (QC-LDPC) codes encoder. The designed QC-LDPC encoder employs a multi-channel parallel
doi:10.3390/s21186266
pmid:34577470
fatcat:cg5egad6kzg3pflkugt7k22a3y