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Survey on Multigrained Reconfigurable Architecture using Parallel Mapping Method
2017
Indian Journal of Science and Technology
Objectives: In previous methodology, only ALU operations are seen with respect to the network on chip with this power and delay is high whereas in present research, Multi-grained reconfigurable architecture is used which reduces power and delay. In this method we can also perform multiple FFT, DCT, FIR and channel encoder. Methods: For execution, the number of instructions is flapped by associating pipelining technique which is splitted in stages. Every stage completes an area of parallely
doi:10.17485/ijst/2017/v10i6/110837
fatcat:eseoaf2g2vbrfajebekoz5frl4