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In deep submicron technology, wire delay is no longer negligible and is gradually dominating the system latency. Some state-of-the-art architectural synthesis flows adopt the distributed register (DR) architecture to cope with this increasing latency. The DR architecture, though allows multicycle communication, introduces extra overhead on interconnect resource. In this paper, we propose the Regular Distributed Register -Global Resource Sharing (RDR-GRS) architecture to enable global sharing ofdoi:10.1109/aspdac.2008.4483933 dblp:conf/aspdac/HuangHHH08 fatcat:5x6xvlagl5bbhljq4kipuegxbu