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Efficient PEEC-based inductance extraction using circuit-aware techniques
Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors
Practical approaches for on-chip inductance extraction to obtain a sparse, stable and accurate inverse inductance matrix K are proposed. The novelty of our work is in using circuit characteristics to define the concept of resistance-dominant and inductancedominant lines. This notion is used to progressively refine a set of clusters that are inductively tightly-coupled. For reasonable designs, the more exact Algorithm 1 yields a sparsification of 97% for delay and oscillation magnitude errors of
doi:10.1109/iccd.2002.1106808
dblp:conf/iccd/HuS02
fatcat:fukfy3wzzbfxngyyxov5xjng7a