Performance modeling for all-optical photonic switches based on the vertical stacking of banyan network structures

Xiaohong Jiang, Pin-Han Ho, S. Horiguchi
2005 IEEE Journal on Selected Areas in Communications  
The scheme of vertical stacking has caught much interest in the design of ultra high-speed communication switches for the past a few years. In particular, the scheme can greatly facilitate the effort of constructing all-optical photonic switches in the event that a Banyan network structure is adopted. A vertically stacked photonic Banyan (VSPB) network can preserve the good properties of the Banyan network structures, such as the small depth and absolute loss uniformity; on the other hand, it
more » ... he other hand, it introduces a significant increase in the hardware cost. Extensive research efforts have been addressed in determining the minimum number of stacked copies (planes) required for a nonblocking VSPB network. However, very few of them focused on the performance of the VSPB networks in terms of blocking probability. Therefore, in this paper, we study the blocking behavior of the VSPB networks and propose a corresponding analytical model under the random routing strategy. The proposed analytical model is designed to fully explore the property of symmetry in Banyan network structures, and can calculate the blocking probability of a VSPB network stage by stage in a recursive manner such that the combinatorial explosion problem is avoided. To verify the proposed model, we conduct extensive simulations, in which the results indicate that our model can accurately describe the blocking behavior of VSPB networks under the random routing strategy and it agrees with the conditions of strictly nonblocking VSPB networks. We find that the proposed analytical model can deeply investigate into the inherent relationship between blocking probability and network hardware cost in terms of the number of planes; as a result, a quantitative guidance for initiating a graceful compromise between blocking probability and hardware cost can be developed based on the analytical model. Our analysis results also show that the hardware cost of a VSPB network can be dramatically reduced by simply allowing a negligible nonzero blocking probability in most of the practical cases. This fact will solidly contribute to the network switch architecture design and enable more practical applications of VSPB networks. . He has published over 50 refereed technical papers in these areas. His research interests include optical switching networks, WDM networks, interconnection networks, IC yield modeling, timing analysis of digital circuits, clock distribution and fault-tolerant technologies for VLSI/WSI. Authorized licensed use limited to: IEEE Xplore. as an Assistant Professor. He is the first author of more than 50 refereed technical papers and the coauthor of a book on optical networking and survivability. Prof. Ho is the recipient of the Best Paper Award and the Outstanding Paper Award from SPECTS'02 and HPSR'02, respectively. Susumu Horiguchi (M'81-SM'95) received the B.Eng., M.Eng., and Ph.D.
doi:10.1109/jsac.2005.851754 fatcat:n7fw4chpl5b33afd5lw2kdkf5u