Top–Down Fabrication of Gate-All-Around Vertically Stacked Silicon Nanowire FETs With Controllable Polarity

Michele De Marchi, Davide Sacchetto, Jian Zhang, Stefano Frache, Pierre-Emmanuel Gaillardon, Yusuf Leblebici, Giovanni De Micheli
2014 IEEE transactions on nanotechnology  
As the current MOSFET scaling trend is facing strong limitations, technologies exploiting novel degrees of freedom at physical and architecture level are promising candidates to enable the continuation of Moore's predictions. In this paper, we report on the fabrication of novel ambipolar Silicon nanowire (SiNW) Schottky-barrier (SB) FET transistors featuring two independent gate-all-around electrodes and vertically stacked SiNW channels. A top-down approach was employed for the nanowire
more » ... he nanowire fabrication, using an e-beam lithography defined design pattern. In these transistors, one gate electrode enables the dynamic configuration of the device polarity (n-or p-type) by electrostatic doping of the channel in proximity of the source and drain SBs. The other gate electrode, acting on the center region of the channel switches ON or OFF the device. Measurement results on silicon show I on /I off > 10 6 and subthreshold slopes approaching the thermal limit, SS ≈ 64 mV/dec (70 mV/dec) for p(n)-type operation in the same physical device. Finally, we show that the XOR logic operation is embedded in the device characteristic, and we demonstrate for the first time a fully functional two-transistor XOR gate. Index Terms-Ambipolar transistor, Bosch process, double-gate, dual-gate, e-beam lithography, gate-all-around (GAA), polarity control, silicon nanowire (SiNW), top-down fabrication, XOR logic gate. 1536-125X
doi:10.1109/tnano.2014.2363386 fatcat:ddok3ovf3fhtpnxnkcbcd2hnby