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A Domain-Specific On-Chip Network Design for Large Scale Cache Systems
2007 IEEE 13th International Symposium on High Performance Computer Architecture
As circuit integration technology advances, the design of efficient interconnects has become critical. On-chip networks have been adopted to overcome scalability and the poor resource sharing problems of shared buses or dedicated wires. However, using a general on-chip network for a specific domain may cause underutilization of the network resources and huge network delays because the interconnects are not optimized for the domain. Addressing these two issues is challenging because in-depthdoi:10.1109/hpca.2007.346209 dblp:conf/hpca/JinKY07 fatcat:uqppu4bfl5dy5agnjkckigrh6m