Circuit clustering for delay minimization under area and pin constraints

H.H. Yang, D.F. Wong
1997 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
We consider the problem of circuit partitioning for multiple-chip implementation. One motivation for studying this problem is the current needs of good p artitioning tools for implementing a circuit on multiple FPGA chips. We allow duplication of logic gates as it would reduce circuit delay. Circuit partitioning with duplication of logic gates is also called circuit clustering. In this paper, we present a circuit clustering algorithm that minimizes circuit delay subject to both area and pin
more » ... traints on each chip, using the general delay model. We develop a repeated network cut technique for nding a cluster that is bounded b y b oth area and pin constraints. Our algorithm achieves optimal delay under either the area c onstraint only or the pin constraint only. Under both area and pin constraints, our algorithm achieves optimal delay in most cases. We outline the condition under which the nonoptimality occurs and show that the condition occurs rarely in practice. We tested our algorithm on a set of benchmark circuits and consistently obtained optimal or near-optimal delays.
doi:10.1109/43.658566 fatcat:mfs4np76qbbaho7u2zzakzewc4