Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density

Milos Stanisavljevic, Frank Kagan Gürkaynak, Alexandre Schmid, Yusuf Leblebici, Maria Gabrani
2007 Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '07  
This paper presents a new approach for assessing the reliability of nanometer-scale devices prior to fabrication and a practical reliability architecture realization. A four-layer architecture exhibiting a large immunity to permanent as well as random failures is used. Characteristics of the averaging/thresholding layer are emphasized. A complete tool based on Monte Carlo simulation for a-priori functional fault tolerance analysis was used for analysis of distinctive cases and topologies. A
more » ... chip CMOS integrated design of the 128-bit AES cryptography algorithm with multiple cores that incorporate reliability architectures is shown. Fault-tolerant architecture, high defect density, reliability of submicron and nanoelectronic systems.
doi:10.1145/1228784.1228837 dblp:conf/glvlsi/StanisavljevicGSLG07 fatcat:fyou2ysafbakzddv4tgki5ikcq