Minimizing the number of delay buffers in the synchronization of pipelined systems
Proceedings of the 28th conference on ACM/IEEE design automation conference - DAC '91
When designing a pipelined digital system, dekay buffers (often implemented as shifr registers) are usually introduced into the system in order to synchronize the various signals impinging on each processing element. That is, to insure that all inputs to a processing block arrive at precisely the same time. Automatic techniques for finding the lengths of such buffers, and their proper points of insertion in the system, have been proposed. They are usually bared on graph-theoretic approaches.
... 31. However, the solution to this synchronization problem is not Imique. so there exist many combinations of buffer locatim and length that can produce overall synchronization in a typical pipelined network. Obviously. it would be beneficial to determine the minimum number of total delay buffer stages necessary to s)mchronize a pipelined system, so that the system hardware cost and complexity can be reduced. In this paper. we present an algorithm to solve this buffer minimization problem. We will show that it can be recast in term of the clarsical minimum cost network flow problem. Hence, the time complexity of our algorithm is polynomial rather than exponential as for the algorithm reported in 141. Our technique is qplicable to system con%aining feedback Imps, but in the interest 4 brevity in this article we will treat only the most common case in which our wderlying system graphs are acyclic. The algorithm has been used in a silicon compiler design environment described in [SI.