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Tree Realizations of Iterative Circuits

Unger

1977
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IEEE transactions on computers
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It is shown how any combinational function that can in a spatial sequence. Note that both Z and Y are funebe described by a flow table-or equivalently-is realizable in it-tions of the inputs and prevous y, exactly as in the case of erative form-can be realized in tree form. The propagation delay sequential circuits. This analogy allows us to use virtually is then proportional to the logarithm of n, the number of inputs, all of the tools developed for sequential circuits. In parwhile the logic
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... arwhile the logic complexity is a linear function of n. These results ar, flowtabletechni que nobap to CUare related to various implementations of high-speed binary adders ticular, flow table techniques can now be applied to CUand a proposed new high-speed adder circuit. ODIC's. For example, the function performed by the binary Index Terms-Adders, binary adders, carry lookahead, combi-. e national circuits, conditional sum, flow tables, high speed arith-adder can be described by the flow table of Fig. 2 . The 1metic units, iterative circuits, modular circuits, semi-groups, variable state assignment in which y = 0 for state 1 and 1 synthesis, tree circuits. for state 2 leads to the circuit of Fig. 1 . Note that exactly the same logic module can be used to build a serial binary adder if we insert a unit delay between the Y and y terminals and feed in the a and b signals synchronously in N ITERATIVE circuit is a circuit constructed time. by interconnecting a set of identical modules or The advantages of CUODIC's over conventional comsubcircuits in a regular array, a concept introduced by bination circuit realizations of the same functions are: Keister, Ritchie, and Washburn [121. Material on this 1) The total amount of logic grows linearly with the subject is in [1, Section 9.6]. An extensive treatment of number of inputs. Thus the number of logic elements certain theoretical aspects is in Hennie's book [2]. needed when there are many inputs is likely to be less than Perhaps the best known and most important example for conventional circuits where the rate of increase is nearly of a function realizable by an iterative circuit is the parallel exponential. binary adder, shown in Fig. 1 in its simplest form. 2) The design process is relatively simple and is essen- The inputs ai and bi represent the ith bits of binary tially independent of the number of inputs. numbers A and B, whose sum is generated as the sequence 3) The form of the overall circuit, being a regular array of bits Z1 thru Zn. (Least significant bits are a" bI and ZI.) of identical modules, is very suitable for implementation The modules, generally called typical cells, in this case are via integrated circuits. combinational circuits realizing the output function Z = 4) Testing, fault detection, and repair are all facilitated a @ b @ y (where @ represents modulo-2 addition), and the by the form referred to above. intercell function Y = M(a,b,y) (where M is the majority There appears to be just one disadvantage inherent in function, whose output is 1 if at least 2 of the 3 inputs equal the iterative approach. Note that for i > j, output signal 1). Zi is in general a function of input signal xj. In particular, This circuit is an example of a combinational, unilateral, Z, is in general a function of xl. Hence there are long paths one-dimensional, iterative circuit (CUODIC). Circuits of through the logic from certain inputs to certain outputs. this type are of considerable practical interest and, fortu-We have here an extreme case of multilevel logic with the nately, there exist powerful methods for analyzing and associated problems of signal attenuation and delay. We synthesizing them. shall not worry about attenuation since modern logic There is a direct analogy between CUODIC's and syncomponents have inherent signal restoration properties. chronous sequential circuits, discovered by Huffman [5]. Delay, however, is sometimes a serious problem. The sequence of input signals in space (aib1,a2b2, * , in With respect to adders in particular, there is a history our example) may be considered as analogous to a time going back at least as far as Babbage [91 of methods for sequence of the same values. Similarly for the output secircumventing the delay problem (see references in Lehquence (Z1,Z2, * *). The intercell signals (the y's) can be man and Burla [11] for more recent efforts). Waite [4] has thought of as representing states in time of a single circuit generalized some of this work to cover all functions realiinstead of states of identical but different circuits arranged zable by CUODIC's. -~~~~~~~~~~~~~~In the next section, a rather simple method is presented Manuscript

doi:10.1109/tc.1977.1674846
fatcat:ve6ea6hnrjd33nwkzbvoabiyrm