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2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)
A power-efficient and speed-enhancing technique for time-interleaved (TI) SAR ADCs that is assisted by a lowresolution flash ADC is presented. The 3 b MSBs achieved from a flash ADC at every clock save two decision cycles from every SAR ADC channel, resulting in a reduced number of time interleaving channels with a total 27% energy saving compared with the energy consumption of a conventional TI SAR ADC . A prototype 6 b 2 GS/s ADC in a 45 nm CMOS consumes 14.4 mW under a 1.2 V supply anddoi:10.1109/asscc.2013.6691037 fatcat:uyhw6fc4c5apvedvdohb5wb7oy