A 6 bit 2 GS/s flash-assisted time-interleaved (FATI) SAR ADC with background offset calibration

Ba-Ro-Saim Sung, Chang-Kyo Lee, Wan Kim, Jong-In Kim, Hyeok-Ki Hong, Ghil-Geun Oh, Choong-Hoon Lee, Michael Choi, Ho-Jin Park, Seung-Tak Ryu
2013 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)  
A power-efficient and speed-enhancing technique for time-interleaved (TI) SAR ADCs that is assisted by a lowresolution flash ADC is presented. The 3 b MSBs achieved from a flash ADC at every clock save two decision cycles from every SAR ADC channel, resulting in a reduced number of time interleaving channels with a total 27% energy saving compared with the energy consumption of a conventional TI SAR ADC . A prototype 6 b 2 GS/s ADC in a 45 nm CMOS consumes 14.4 mW under a 1.2 V supply and
more » ... V supply and achieves 5.2 ENOB Nyq with a background offset calibration. I. 978-1-4799-0280-4/13/$31.00 c 2013 IEEE
doi:10.1109/asscc.2013.6691037 fatcat:uyhw6fc4c5apvedvdohb5wb7oy