The potential of functional scaling

A. Chin, S.P. McAlister
2005 IEEE Circuits & Devices  
T he relentless progress of silicon technology in the last few decades has been astounding, owing to device scaling. The characteristic lengths associated with successive generations of the technology have decreased, producing higher performance devices and circuits. At various times, people have predicted the end of scaling because of apparent barriers, but these barriers have fallen thanks to the ingenuity of the scientists and engineers involved in the technology. This has occurred through
more » ... velopments and changes in device design, the introduction of new materials, improved processing technologies and tools-both engineering and simulation-and other innovative approaches. The resulting increases in the densities of devices and their functionality in circuits now make the issue of power dissipation, both static and dynamic, a serious constraint to future scaling advances. In this article, a new very large scale integration (VLSI) structure is proposed and demonstrated to address these issues, using the three-dimensional (3-D) integration of high performance Ge-oninsulator (GOI) field effect transistors above conventional interconnects and Si devices. The basic building-block of silicon technology, the metal-oxide-semiconductor field-effective transistor (MOSFET), shown schematically in Figure 1 , has been down-scaled in its dimensions in successive technology generations. This scaling has been remarkably successful and sustained, yielding increased performance and circuit complexity but not at increased cost. Thus, scaling has been the driving force in Si microelectronics and will continue to be so [1], [2] . This has had a significant down side: the enormous capital costs of new state-of-the-art processing lines, which now have to handle 300-mm diameter wafers at a high volume to make them economically viable. Indeed, scaling might ultimately be limited as much by economics as by physics. Scaling not only yields a higher integration density but also a higher transistor drive current and density for faster switching speeds (I d /C load V d ) in integrated circuits (ICs). The reduction in device dimensions increases the probability of tunneling, for example through the gate oxide, between the source and drain, and between the body and drain. Since the drive current of a sub-100 nm scale MOSFET is proportional to the gate dielectric capacitance/area (C ox = ε 0 κ/ t ox ), a higher drive current is obtained by scaling down the oxide thickness t ox . This provides more efficient channel charge control by the gate voltage; i.e., higher transconductance. Unfortunately, this down-scaling of t ox (∼ 1.2 nm thickness in present technologies) also leads to a higher leakage
doi:10.1109/mcd.2005.1388766 fatcat:kutsxwyf6zazdhzedvtgkw265i