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Cache-conscious structure layout
1999
Proceedings of the ACM SIGPLAN 1999 conference on Programming language design and implementation - PLDI '99
Hardware trends have produced an increasing disparity between processor speeds and memory access times. While a variety of techniques for tolerating or reducing memory latency have been proposed, these are rarely successful for pointer-manipulating programs. This paper explores a complementary approach that attacks the source (poor reference locality) of the problem rather than its manifestation (memory latency). It demonstrates that careful data organization and layout provides an essential
doi:10.1145/301618.301633
dblp:conf/pldi/ChilimbiHL99
fatcat:nop647je5ffibjp5fux3ugnjai