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Using simulation and satisfiability to compute flexibilities in Boolean networks
2006
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simulation and Boolean satisfiability (SAT) checking are common techniques used in logic verification. This paper shows how simulation and satisfiability (S&S) can be tightly integrated to efficiently compute flexibilities in a multilevel Boolean network, including the following: 1) complete "don't cares" (CDCs); 2) sets of pairs of functions to be distinguished (SPFDs); and 3) sets of candidate nodes for resubstitution. These flexibilities can be used in network optimization to change the
doi:10.1109/tcad.2005.860955
fatcat:qfd6n32sczdndh7msjnij65voy