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ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)
A pipeline floating point arithmetic logic unit (ALU) design using VHDL is introduced. The novelty of the ALU is it gives high performance through the pipelining concept. Pipelining is a technique where multiple instruction executions are overlapped. In the top-down design approach, four arithmetic modules: addition, subtraction, multiplication, and division: are combined to form the floating-point ALU. Each module is divided into smaller modules. Two bits selection determines which operationdoi:10.1109/smelec.2002.1217807 fatcat:kxwsl6gghjfmlom4cjws5ml7yu