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Fault Detection Architectures for Field Multiplication Using Polynomial Bases
2006
IEEE transactions on computers
In many cryptographic schemes, the most time consuming basic arithmetic operation is the finite field multiplication and its hardware implementation for bit parallel operation may require millions of logic gates. Some of these gates may become faulty in the field due to natural causes or malicious attacks, which may lead to the generation of erroneous outputs by the multiplier. In this paper, we propose new architectures to detect erroneous outputs caused by certain types of faults in
doi:10.1109/tc.2006.147
fatcat:exrsfrdxsfae5m7pcb6qrbyhj4