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Multi-level logic minimization using implicit don't cares
1988
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
This paper describes a new approach for the minimization of multilevel logic circuits. We define a multilevel representation of a block of combinational logic called a Boolean network. We propose a procedure, ESPRESSO-MLD, to transform a given Boolean network into a prime, irredundant, and "R-minimal" form. This procedure rests on the extension of the notions of primality and irredundancy, previously used only for two-level logic minimization, to combinational multilevel logic circuits. We
doi:10.1109/43.3211
fatcat:trn3cijzczcrtfkirplczefuo4