Energy-aware mapping for tile-based NoC architectures under performance constraints

Jingcao Hu, Radu Marculescu
2003 Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC  
In this paper, we present an algorithm which automatically maps the IPs/cores onto a generic regular Network on Chip (NoC) architecture such that the total communication energy is minimized. At the same time, the performance of the mapped system is guaranteed to satisfy the specified constraints through bandwidth reservation. As the main contribution, we first formulate the problem of energy-aware mapping, in a topological sense, and then propose an efficient branch-and-bound algorithm to solve
more » ... algorithm to solve it. Experimental results show that the proposed algorithm is very fast and robust, and significant energy savings can be achieved. For instance, for a complex video/audio SoC design, on average, 60.4% energy savings have been observed compared to an ad-hoc implementation.
doi:10.1145/1119772.1119818 dblp:conf/aspdac/HuM03 fatcat:twwyyzokmbhhvc5wx34wr6jo4i