25th ACM/IEEE, Design Automation Conference.Proceedings 1988.
A parallel algorithm is proposed for solving the problem of channel and switchbox routing in the design of VLSl chips. The algorithm is suitable for implementation on a shared-memory multiprocessor environment. Our approach does not impose restrictions on the channel type (such as fix or variable channel widths) and the number of available layers. The algorithm contains three major phases: I) dividing the channel into several regions by selecting some columns, 2) assigning tracks to nets of thedoi:10.1109/dac.1988.14747 fatcat:lrdttrznlvetpl4ytw7cls7bla